1. Field of Invention
The present invention relates an integrated circuit. More particularly, the present invention relates to a memory device.
2. Description of Related Art
In recent years, the performance demands on consumer electronic products, such as mobile phones and tablets, are increasing, which results in the need of higher clock speed and more accurate signal timings for a proper operation.
Memory devices are widely used in the consumer electronic products, such as a dynamic random access memory (DRAM) that has been developed to provide faster operation time. DRAM typically performs read/write operations with a system clock signal generated from a delay lock loop circuit. In order to meet the requirement in high-speed operation, the power consumption of the delay locked loop circuit increases. However, DRAM can operate certain operations without the system clock signal, when DRAM operates in standby conditions. In these operations, the delay locked loop circuit causes an unnecessary consumption of power.
Therefore, a heretofore-unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.